(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of small contact formation combined with etchback planarization in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuits, a dielectric layer is deposited over a semiconductor substrate containing semiconductor device structures such as gate electrodes and source and drain regions. It is desirable to planarize the dielectric layer. Planarization can be a complex or expensive process. Contact openings are made through the dielectric layer to the underlying semiconductor device structures to be contacted. A conducting layer is deposited into the contact openings and patterned to complete the desired electrical connections. The process of making a small contact, on the order of 0.1 to 0.5 microns, is limited by lithography constraints or is a complex process.
U.S. Pat. No. 4,775,550 to Chu et al teaches a spin-on-glass and oxide etchback process.